
2011 Microchip Technology Inc.
DS39932D-page 195
PIC18F46J11 FAMILY
TABLE 11-2:
REGISTERS ASSOCIATED WITH PMP MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PMPIF(2)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
PIE1
PMPIE(2)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
IPR1
PMPIP(2)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
PMCONH(2)
PMPEN
—
ADRMUX1 ADRMUX0
PTBEEN
PTWREN
PTRDEN
PMCONL(2)
CSF1
CSF0
ALP
—
CS1P
BEP
WRSP
RDSP
PMADDRH(1,2)/
—
CS1
Parallel Master Port Address High Byte
PMDOUT1H(1,2) Parallel Port Out Data High Byte (Buffer 1)
PMADDRL(1,2)/ Parallel Master Port Address Low Byte
PMDOUT1L(1,2) Parallel Port Out Data Low Byte (Buffer 0)
PMDOUT2H(2)
Parallel Port Out Data High Byte (Buffer 3)
PMDOUT2L(2)
Parallel Port Out Data Low Byte (Buffer 2)
PMDIN1H(2)
Parallel Port In Data High Byte (Buffer 1)
PMDIN1L(2)
Parallel Port In Data Low Byte (Buffer 0)
PMDIN2H(2)
Parallel Port In Data High Byte (Buffer 3)
PMDIN2L(2)
Parallel Port In Data Low Byte (Buffer 2)
PMMODEH(2)
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
PMMODEL(2)
WAITB1
WAITB0 WAITM3 WAITM2
WAITM1
WAITM0
WAITE1
WAITE0
PMEH(2)
—PTEN14
—
PMEL(2)
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
PMSTATH(2)
IBF
IBOV
—
IB3F
IB2F
IB1F
IB0F
PMSTATL(2)
OBE
OBUF
—
OB3E
OB2E
OB1E
OB0E
PADCFG1
—
RTSECSEL1 RTSECSEL0 PMPTTL
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used during PMP operation.
Note 1:
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and
addresses, but have different functions determined by the module’s operating mode.
2:
These bits and/or registers are only available in 44-pin devices.